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A cache where the cache location for a givenaddress is determined from the middle address bits. If thecache line size is 2^n then the bottom n address bitscorrespond to an offset within a cache entry. If the cachecan hold 2^m entries then the next m address bits give thecache location. The remaining top address bits are stored asa "tag" along with the entry.In this scheme, there is no choice of which block to flush ona cache miss since there is only one place for any block togo. This simple scheme has the disadvantage that if theprogram alternately accesses different addresses which map tothe same cache location then it will suffer a cache miss onevery access to these locations. This kind of cacheconflict is quite likely on a multi-processor. See alsofully associative cache, set associative cache.